The present invention relates to a bias voltage generator for a monolithic integrated circuit with a plurality of I.sup.2 L current sources each consisting of a plurality of I.sup.2 L double-collector transistors having one common injector and being individually connected in series with the emitter of a corresponding bias voltage transistor whose base zone is connected to a bias voltage lead. Such a type of bias voltage generator is used in the integrated I.sup.2 L circuit serving the superposition of audio frequency signals as disclosed in the applicant's earlier U.S. Patent Application Ser. No. 101,314 for adjusting the operating point of the I.sup.2 L current sources. The bias voltage generator according to the invention, however, is also suitable for use with digital-to-analog converters of similar configuration employing I.sup.2 L current sources consisting of a plurality of I.sup.2 L multi-collector transistors having one common injector.
The bias voltage generator in the integrated I.sup.2 L circuit according to the aforementioned earlier proposal, as well as in similarly designed digital-to-analog converters serves the exact balancing of the output currents. In conventional large scale production of integrated solid state circuits on semiconductor wafers, for separation into individual units, fluctuations which occur throughout the individual semiconductor wafers cause the medium output currents of the integrated circuits on a semiconductor wafer to deviate from the mean value of other semiconductor wafers.
Uniformity is required of the output currents of each of the many integrated circuits manufactured on a semiconductor wafer. Consequently, the yield of the integrated circuit is reduced as a result of the fluctuations of the following parameters from the respective mean values of one or several semiconductor wafers:
1. fluctuations of the medium alpha values of the injector transistors, PA1 2. fluctuations of the medium B-values of the I.sup.2 L transistors, PA1 3. fluctuations of the medium output resistances of the I.sup.2 L transistors, and PA1 4. fluctuations of the medium pairing values of alpha-B-values.
Relative thereto, it is assumed that the aforementioned fluctuations within the individual integrated circuits are of the minimum nature which can be achieved in ordinary commercial manufacturing without affecting the yield when production is carried out in accordance with the present state of the art.